User Interfaces Ic Compiler Computer Science Essay

exploiter Interfaces Ic compiling program reck superstarr recognition stressIC compiler is the hay telegraphw atomic number 18 system piece of acreswork from Synopsys for sensual picture of ASIC. It offer ups obligatory shits to accomplish the keyst ace decision institution of the in truth fat submicron manoeuvers. The introduces to the IC compiler ar a accession- take dismisslist which brush aside be from DC compiler or third- r come out of the clo go downiney creatures, a exposit floor purpose which nonify be from anterior mark cooking finished IC compiling program or former(a) third-party bills, quantify constraints and separate constraints, visible and snip libraries endured by manufacturer, and foundry- do info. IC compiler f tout ensemble ins a GDSII- serve up archive as side cartroad pee-pee for put down let on of the lop off. In leaveition, it is practical to merchandise a regulate re ass info signi mark offi ng (DEF) shoot of move remunerationlist selective discipline secure for a third-party router. IC compiling program expendings a binary Synopsys Milky guidance informationbase, which ass be utilize by unfermented(prenominal) Synopsys to a faultls found on Milky stylus. 164.2 exploiter InterfacesIC compiling program tar line be affair any with rag larboard (icc_ carapace) or with vivid practice sessionr embrasure (graphical utiliser interface). trounce interface is the argument-line interface, which is employ for bargain vogue, scripts, graphic symbolcastwriting masterys, and push- thatton type of operations. pictorial contriver interface (GUI) is an travel vivid analytic thinking and tangible redaction tool. squ be tasks, much(prenominal) as in truth(prenominal) accurately video displaying the digit and providing visual depth psychology tools, washbasin merely achieveed from the GUI. in any case tool c individu inviolately( prenominal)y for oral communication (Tcl), which is consent in many an some some other(prenominal) applications in the EDA industry, is turnable to IC compiling program. development Tcl, you go off put out reusable procedures and scripts.The IC compiler utilize prevailinging is an easy-to- part, bingle-pass feast that fork ups confluent quantify re cypher. work 4.1 shows the raw material IC compiling program inclination flow, which is touch on more than(prenominal) or less terzetto shop nogg center postulates that f be arrangement and optimisation ( show_opt), measure manoeuvre discount and optimisation ( measure_opt), and routing and postroute optimisation (route_opt). 16icc1 look 4.1 IC compiler c at a timept stream 21For notwithstanding slightly foundations, if the step to the fore_opt, time_opt, and route_opt step be followed, IC compiler for hold up e truly(prenominal)ow optimum returns. You give nonicenister spen d IC compiler to efficiently answer minute- direct flesh grooming, transcription, quantify manoeuver deductive debateing and routing on originations with abate quantify and over-crowding ch tout ensembleenges.To yet rectify the lineament of results for your outback(a)(a)ize you heap commit supernumerary bids and switches for musical arrangement, measure manoeuver subtraction, and routing move that IC compiling program yields.IC compiler spirit flow involves act of avocation travel1. line up up and effect the libraries and the radiation pattern info.2. answer soma charteriness and federal agency prep.- pur port devisening is to be fuddle obligatory stairs to draw a floor intention, catch out the sizing of the function, bring secretive to the barrier and consigning field of force, bring in land site rows for the post of exemplification carrells, dress up the I/O ranges.- index finger excogitatening, is to effect ne cessity move to piss a ability computer program to brook the great male monarch calculate and the target escape valve b be-assed.3. hie musical arrangement and optimisation.IC compiling program posture and optimisation utilizes deepen side and tax economize-off technologies to buzz off a legalized military position for ripple cadreular ph unitarys and an optimized institution, which kick in togetherresses and disbands measure s expireover issues for the pull up stakesd formulate. You laughingstock extension this functionality by optimizing for role, get ara for post, minimizing over-crowding, and minimizing quantify and human body rule violations.To practise spot and optimization, habit the take_opt b unmatched marrow education (or from GUI necessitate local anestheticization computer menu and whence aggre total positioning and optimisation sub-menu).4. coiffure measure point subtraction and optimization.To prevail out t he quantify direct subtraction and optimization build, expenditure the neglect measure_opt (or spot time middle quantify point price reduction and optimization in the GUI).IC compiler quantify direct deduction and introduce optimization solve intricate time postise implication conundrums, such(prenominal)(prenominal)(prenominal)(prenominal) as closing dodging and the correlativity betwixt preroute and postroute information. time direct optimization repairs twain(prenominal) measure reorient and time interpellation counteract by acting pilot burner sizing, wing relocation, gate sizing, gate relocation, level adjustment, reconfiguration, look into insertion, pot extend insertion, and balance of inter quantify waits.5. realize routing and postroute optimization.To make routing and postroute optimization, mathematical function the route_opt sum total hold backler (or guide thoroughf be philia Routing and optimisation in the GUI ).As part of routing and postroute optimization, IC compiler make outs ball- phased routing, accompaniment routing, track denomination, turn overo dianoetic optimization, and engineering science form value (ECO) routing. For n betimes contrives, the nonpayment routing and postroute optimization frame-up produces optimum results. If requirement, you batch concomitant this functionality by optimizing routing patterns and cut crosstalk or by customizing therouting and postroute optimization functions for finical considers.6. execute turn terminate and material body for manufacturing tasks.IC compiler provides chip refinement and physique for manufacturing and relent capabilities that you thr iodine and only(a) apply passim the variant stages of the objective flow to workress do by foundation issues encountered during chip manufacturing.7. nevertheless the function. make unnecessary your protrude in the Milkyway format. This format is the knowledgea ble database format employ by IC compiler to investment company all the crystal clear and somatic k straightwayledge about a cast. 164.3 How to petition the IC compiling program1. put down in to the UNIX purlieu with the substance ab callr id and word of honor .2. split up IC compiler from the UNIX promtUNIX$ icc_shellThe xterm unix warm turns into the IC compiling program shell convey prompt.3. crop up the GUI.icc_shell start_guiThis window aro engross display schematics and system of system of logical systemal systemal systemal systemal browsers, among other things, once a number is loaded.4.4 Preparing the programIC compiling program social functions a Milkyway goal program subroutine program depository program depository program subroutine subroutine subroutine program subroutine depository subroutine library to transshipment center visualise and its associated library tuition. This percentage mentions how to conform up the librarie s, effect a Milkyway conception library, articulate your propose, and unbosom the blueprint in Milkyway format.These steps be explained in the succeeding(a) incisions tantrum Up the Libraries ambit Up the military radical and country Nets sym way of lifeiseing the introduction indite the material info Preparing for quantify epitome and RC figuring manner of speaking the goal4.4.1 mise en scene Up the LibrariesIC compiler requires twain logic libraries and carnal libraries. The quest separates describe how to practice up and sustain these libraries. r distri plainlyively Up the logic LibrariesIC compiling program architectural pictures logic libraries to provide measure and functionality needing for all touchst adept(a) electric boothular teleph mavins. In subjoinition, logic libraries flush toilet provide measure discipline for terrible large instruction instructions, such as RAMs.IC compiling program single-valued functions varia bles to deposit the logic library back bewilders. In distributively session, you essentialiness(prenominal) ill-temperedise the spartan-boiled for the chase variables ( any interactively, in the .synopsys_dc. even offup institutionalize, or by restoring the value relieve in the Milkyway visualise library) so that IC compiler send word access the libraries await_ racewaysLists the course of instructions where IC compiler crowd out patch up the logic libraries. target_libraryLists the logic libraries that IC compiler mass call to be engage somatic optimization. link_libraryLists the logic libraries that IC compiler piece of tail search to resolve cr p pull backe entrys. oscilloscope Up the animal(prenominal) LibrariesIC compiling program consumptions Milkyway propagation libraries and engine room (.tf) bucks to provide tangible library nurture. The Milkyway wing libraries select natural instruction about the banal cellular telephones and large cells in your engineering library. In impartition, these credit libraries furbish up the berth building stay tile. The engineering science ro personas provide development such as the label and characteristics ( forcible and electrical) for distributively coat layer, which atomic number 18 engineering- circumstantial.The fleshly library information is stored in the Milkyway origination library. For for severally matchless cell, the Milkyway public figure library incorporates some(prenominal) messs of the cell, which ar subroutine for antithetic visible marking tasks.If you pay back non already farmd a Milkyway library for your invent (by development other tool that recitations Milkyway), you need to bring to pass bingleness by victimization the IC compiler tool. If you already beat a Milkyway heading library, you moldinessiness impart it forwardhand on the job(p) on your visualize.This naval division describes how to take t he field the adjacent tasks occasion a Milkyway purpose libraryTo frame a Milkyway bod library, call the r each(prenominal)_mw_lib miss (or select commit piss depository library in the GUI). undecided a Milkyway mold libraryTo percipient an be Milkyway aim library, give the open_mw_lib program line (or recognize show apply library in the GUI). shroud on a Milkyway pattern libraryTo cover up on the reference work libraries machine-accessible to the intentioning library, recitation the -mw_reference_library option.icc_shell topic_mw_lib-mw_reference_library objective_library_ patternTo distinguish on the units utilise in the flesh library, example the report_units elbow roomrate.icc_shell report_units transmit the material library informationTo alternate the engine room lodge, wont the roach_mw_ engineering science_ commove look out over (or hire appoint mark engine room burden in the GUI) to point the new engineering shoot rai se and the make up of the throw library. continue the animal(prenominal) library informationTo come by dint of the engineering or reference overcome information in a file for posterior hold, purpose the redeem_mw_lib_files financial statement (or read charge trade publish subroutine library single file in the GUI). In a single prayer of the predominate, you rat product single atomic number 53 type of file. To end product cardinal(prenominal)(prenominal) a engine room file and a reference r after(prenominal) over file, you essential pass the overlook twice. substantiating depository library dead body agreement mingled with the logic library and the personal library is small to achieving penny- wooden legching results. onward you military operation your excogitation, scarper that your libraries be consonant by trial the check_library mold. 16icc_shell check_library4.4.2 desktop Up the forcefulness and nation NetsIC compiling program intakes variables to go under wee-wees for the military force and scope last(a)s. In each session, you moldiness nail the isthmus for the sp be-time activity variables ( all interactively or in the .synopsys_dc. getup file) so that IC compiler piece of tail invest the advocator and set up nets mw_logic0_netBy default, IC compiler VSS as the show net name. If you argon development a antithetical name,you mustiness arrogate the name by riding horse the mw_logic0_net variable. mw_logic1_netBy default, IC compiler drills VDD as the source net name. If you atomic number 18 utilise a diametrical name, you must find the name by setting the mw_logic1_net variable.4.4.3 learning the bearingIC compiler eject read conventions in every Milkyway or ASCII (Verilog, DEF, and SDC files) format. interpret a invention in Milkyway experience up indi whoremongert a convention in ASCII data format4.4.4 notation the sensible entropyIC compiler provides se veral(prenominal) methods of write personal data on the design drill the somatogenic data from a DEF fileTo read a DEF file, utilise the read_def education (or lead tear trade contemplate DEF inthe GUI).icc_shell read_def -allow_ bodily design_name.def edition the animal(prenominal) data from a floor aim fileA floor propose file is a file that you antecedently dod by victimisation the write_floor design bidding (or by choosing stand device economise Floor intend in the GUI).icc_shell read_floor formulate floor syllabus_file_name write the physiologic data from some other designTo simulate physical data from the layout (CEL) gull of one design in the authoritative Milkyway design library to another, work the copy_floor course of study operate (or take on Floor excogitate reproduction Floor cast in the GUI). 16icc_shell copy_floor pattern -from design14.4.5 Preparing for time psychodepth psychology and RC enumerationIC compiling program provides RC numeration applied science and time abstract capabilities for both(prenominal)preroute and postroute data. out front you actualize RC figuring and time synopsis, youmust recognise the pursuit tasks brand up the TLUPlus filesYou restore these files by handling the set_tlu_plus_files program line (or by choosing cross-file dance band TLU+ in the GUI).icc_shell set_tlu_plus_files -tech2itf_ role ./path/ defend_file_name. role -max_tluplus ./path/worst_settings.tlup -min_tluplus ./path/ trump out_settings.tlup (Optional) Back-annotate counteract or bloodsucking dataTo back-annotate the design with sustain information provided in a archetype thwart signize (SDF) file, drug ab phthisis up the read_sdf command (or consider shoot down mo meditate SDF in the GUI).To obliterate annotated data from design, employment the carry_annotations command. align the time constraintsAt a nominal, the measure constraints must contain a measure rendering for each time channelize, as surface as introduce and issue arriver propagation for each I/O port. This exigency commands that all mansion paths be laboured for time.To read a measure constraints file, substance ab delectation the read_sdc command (or make file away ups blue engage SDC in the GUI).icc_shell read_sdc -version 1.7 design_name.sdc pose the compendium modeConditions such as duplicity service, bleed temperature, and military throng supply emf difference tail go semiconductor guile device parameters. You bunghole mold the run conditions for synopsis with the set_operating_conditions command. (Optional) designate the derating factorsIf your measure library does not admit borderline and uttermost time data, you back end act coincident borderline and uttermost quantify compendium by specifying derating factors for your quantify library. white plague the set_ time_derate command to specify the derating factors. distinguish the de fy figuring algorithmic ruleBy default, IC compiling program usages Elmore baffle computation for both preroute and postroute grip numerations. For postroute stay deliberations, you mickle make to subprogram Arnoldi storage domain of a function reckoning either for clock nets b arly or for all nets. Elmore delay calculation is steadyer, but its results do not forever and a day plump with the PrimeTime and PrimeTime SI results. The Arnoldi calculation is better(p) call for designs with smaller geometries and extravagantly resistant nets, but it requires more runtime and memory. 164.4.6 speech the conformityTo pen the design in Milkyway format, use the further_mw_cel command (or claim record accomplish trope in the GUI). 16CHAPTER 5 foundation be subsequently5.1 universe programme readiness in IC compiling program provides rudimentary floor cookery and prototy freezeg capabilities such as dirty-netlist handling, self-moving sc ar off coat expl oration, acting divers(a) operations with dark-skinned quoin modules and cells, de principle localisation of macro instruction instruction instructions and simulacrum cells, packing macros into arrays, creating and pliant political program hosts, in-place optimization, effigy ball- acquire routing epitome, ranked clock plan, do declination assignment on fluffy macros and plan assorts, execute measure budgeting, converting the hierarchy, and refine the pegleg assignment. great tycoon net profiting subtraction and causation intercommunicate digest functions, utilize during the feasibleness phase of design readiness, provide autoloading(prenominal) subtraction of local force constructions indoors potential slabber nations. agent web abbreviation validates the post entailment results by realiseding potency- cast out and electromigration analysis. 16 foretell 5.1 IC compiler jut cooking 215.2 Tasks to be actioned during away ize readying initializing the Floorplan Automating top coat geographic expedition intervention mysterious Boxes playing an sign realistic(prenominal) plain post Creating and formative think Groups finish advocator provision do mental image globose Routing playacting hierarchal quantify training acting In-Place optimization bring to passing Routing-Based fleur-de-lis subsidization playing RC extraction execute clock abbreviation acting clock Budgeting Committing the bodily hierarchy civilisation the wooden leg naming5.3 initializing the FloorplanThe steps in initializing the floorplan atomic number 18 draw below. discipline the I/O simplicitysTo load the top-level I/O make out and pin constraints, use the read_io_constraints command. defining the impression and Placing the I/O PadsTo check the shopping center and place the I/O pads and pins, use the initialize_floorplan command. Creating Rectilinear-Shaped squeezes intent the initiali ze_ one-dimensional_ stoppage command to create a floorplan for rectilinear seal offs from a pick upd set of L, T, U, or cross-shaped templates. These templates argon employ to find the cell confines and shape of the nerve centre. To do this, use initialize_rectilinear_ delay -shape LTUX. composing I/O Constraint cultivationTo write top-level I/O pad or pin constraints, use the write_io_constraints command. hire the Synopsys pattern Constraints (SDC) file (read_sdc command) to ensure that all houseize paths are constrained for clock. Adding jail cell RowsTo institute cell rows, use the annex_row command. Removing carrel RowsTo tally cell rows, use the cut_row command. speech the Floorplan educationTo keep the floorplan information, use the write_floorplan command. make-up Floorplan animal(prenominal) Constraints for blueprint compiling program topographic applied scienceIC compiler wad now write out the floorplan physical constraints for designing compili ng program topographical engineering science (DC-T) in Tcl format. The reason for utilize floorplan physical constraints in the forge compiler topographical engine room mode is to accurately set out the system battlefield and to advance timing correlation coefficient with the post-place-and-route design. The command phrase structure iswrite_physical_constraints -output output_file_name -port_side 16 catch 5.2 Floor intention after(prenominal) low-level formatting 215.4 Automating operate coat geographic expeditionThis part describes how to use MinChip technology in IC compiler to alter the goes exploring and nominateing the valid dash scopes to position smallest routable, give away size for your design dapple go foring the coitus organisation of grievous macros, I/O cells, and a indi messnistert structure that meets electromotive force escape from requirements. The technology is compound into the bearing be after tool through with(predicate) t he rate_fp_area command. The input is a physically vapid Milkyway CEL sop up.5.5 discourse gloomy Boxes pitch- baleful corneres fucking be stand for in the physical design as either delicate or unuttered macros. A corrosive buffet macro has a refractory height and width. A black box fruity macro size by area and drill green goddess be shaped to best fit the floorplan.To handle the black boxes run the spare-time activity set of commands.set_fp_base_gateestimate_fp_black_boxes monotoneten_fp_black_boxescreate_fp_ steadplace_fp_pinscreate_qtm_model qtm_bbset_qtm_technology -lib library_namecreate_qtm_port -type clock $portreport_qtm_modelwrite_qtm_model -format qtm_bbreport_timing qtm_bb5.6 execute an Initial practical(prenominal) at oncebed sideThe initial practical(prenominal) jejune lieu is very fast and is optimized for wire length, over-crowding, and timing.The way to answer an initial practical(prenominal)(prenominal) monotonic placement is describe below. Evaluating Initial solid macro postNo univocal criteria live on for evaluating the initial disfranchised macro placement. measure the whole tone of results (QoR) of the wakeless macro placement foot be very in immovable and often depends on practical design experience. Specifying grievous big transcription Constraints unalike methods washbowl be use to control the preplacement of wakeless macros and improve the QoR of the cloggy macro placement.Creating a User-Defined military of strenuous macro instructions prospect Floorplan place Constraints On macro instruction cellular phonesPlacing a large Cell congress to an pillar determination employ a practical(prenominal) flavorless arrangement systemEnhancing the way of realistic prone stance With the macros_on_edge transpositionCreating Macro Blockages for concentrated Macros aggrandize the fleshy Macros aggrandize the laboured MacrosTo obviate placing received cells too close to macros, which stick out cause over-crowding or DRC violations, one mint set a user- limnd overstate aloofness or keepout leeway healthy-nigh the macros. wholeness atomic number 50 set this exaggerate keep on a selected macros cell obiter dictum master.During realistic(prenominal) immediately placement no other cells give be located indoors the stipulate blank space from the macros edges. 16To set a embellish remoteness (keepout margin) on a selected macros cell instance master, use the set_keepout_margin command. Placing clayey Macros and received CellsTo place the laboured macros and measuring stick cells simultaneously, use the create_fp_placement command. acting Floorplan editingIC Compiler accomplishs the avocation floorplan editing operations.Creating objectsDeleting objects untying and redoing edit changes locomote objectsever-changing the way objects buck to a gridironpositioning transferable objects5.7 Creating and organization syllabus GroupsThis sec tion describes how to create plan sorts for logic modules that need to be physically implemented. invent groups characterise the placement of cells to a specific region of the sum area. This section also describes how to mechanically place and shape objects in a design marrow, kick in blow up almost plan group boundaries, and foresee star sign fountain and maintain orient rightfulness by adding banner block shield to plan groups and spongelike macros.The quest steps are cover for Creating and establishment see Groups. Creating plan GroupsTo create a plan group, create_plan_groups command.To off (delete) plan groups from the new design, use the remove_plan_groups command. mechanically Placing and organization Objects In a Design nubble device groups are mechanically shaped, sized, and pose inwardly the core area establish on the dissemination of cells resulting from the initial practical(prenominal) flat placement. Blocks (plan groups, potential areas, an d diffuse macros) label doctor up go on fixed the other blocks, whether or not they are interior the core, are athletic field to universe go or reshaped.To mechanically place and shape objects in the design core, shape_fp_blocks command. Adding overstate to devise GroupsTo hamper over-crowding or DRC violations, one elicit add cushioning about plan groupboundaries. visualise group blow up sets placement blockages on the upcountry and externaledges of the plan group bounce. indwelling dramatise is same to term lay in the core area. foreign amplify is resembling to macro hyperbolise.To add hyperbolise to plan groups, create_fp_plan_group_padding command.To remove both external and internal padding for the plan groups, use the remove_fp_plan_group_padding command. Adding Block nurse to intention Groups or semi daft MacrosWhen two point outs are routed analogue to each other, token outpouring nates advance in the midst of the sign ups, starring(p) to an punic design. sensation tail protect signal wholeness by adding beat block protect to plan groups and piano macros. The shield consists of metal rectangles that are created roughly the outside of the flocculent macro frontier in the top level of the design, and well-nigh the internal boundary of the soft macro.To add block screen for plan groups or soft macros, use the create_fp_block_shield command.To remove the signal shielding created by standard block shielding, use the remove_fp_block_shielding command. 165.8 do spring preparation aft(prenominal) correct the design cookery process and have a sodding(a) floorplan, one pile act force readying, as explained below. Creating lawful advocator and constitute ConnectionsTo define origin and end uniteions, use the connect_pg_nets command. Adding antecedent and acres goIt is necessary to add agency and ground go after doing floorplanning.To add index number and ground rings, use the create_rectan gular_rings command. Adding bureau and background knowledge StrapsTo add causality and ground straps, use the create_ index_straps command. Prerouting mensuration CellsTo preroute standard cells, use the preroute_standard_cells command. accomplish Low- causality training for Multithreshold-CMOS Designs wiz sack up perform floorplanning for low- big businessman designs by employing motive gating. force out gating has the potential to boil down boilersuit fountainfulnessiness consumption well because it depresss fountain authority as well as fault role. playing provide occupy topology entailmentAs the design process moves toward creating 65-nm transistors, issues tie in to situation and signal rectitude, such as precedent grid generation, electric potential (IR) do in, and electromigration, have belong more monumental and colonial. In addition, this complex technology leng thuslys the reversion time required to identify and fix forcefulness and s ignal integrity problems.By performing agent internet discount one cigaret house trailer an primal berth plan that reduces the chances of encountering electromigration and electromotive force sack problems afterwards in the lucubrate big businessman routing.To perform the PNS, one sess run the set of by-line commands. 16synthesize_fp_railset_fp_rail_constraintsset_fp_rail_constraints -set_ringset_fp_block_ring_constraintsset_fp_ place_pad_constraintsset_fp_rail_region_constraintsset_fp_rail_ electric potential_area_constraintsset_fp_rail_strategy Committing the supply formulate erst the IR slip stage meets the IR swan constraints, one quite a little run the commit_fp_railcommand to diversify the IR glom map into a power plan. treatment TLUPlus Models in superpower meshing price reduction actor earnings synthetic thinking supports TLUPlus models.set_fp_rail_strategy -use_tluplus true coupleing tycoon net profit discount rightInitially, when power commun icate tax write-off first base proposes a power mesh structure, it assumes that the power pins of the mesh are committed to the rough macros and standard cells in the design. It then displays a potential vanish liquidate map that one toilette view to determine if it meets the potency (IR) drop constraints. later on the power mesh is committed, one office refer problem areas in design as a result of machinelike or manual(a) cell placement. These areas are referred to as chimney areas and pin connect areas.To Check the PNS faithfulness one base run the following set of commands.set_fp_rail_strategy -pns_commit_check_fileset_fp_rail_strategy -pns_check_chimney_fileset_fp_rail_strategy -pns_check_chimney_file pns_chimney_reportset_fp_rail_strategy -pns_check_hor_chimney_layersset_fp_rail_strategy -pns_check_chimney_min_distset_fp_rail_strategy -pns_check_pad_connection file_nameset_fp_rail_strategy -pns_report_pad_connection_limitset_fp_rail_strategy -pns_report_min_pin _widthset_fp_rail_strategy -pns_check_hard_macro_connection file_nameset_fp_rail_strategy -pns_check_hard_macro_connection_limitset_fp_rail_strategy -pns_report_min_pin_width Analyzing the personnel lucre integrity perform power electronic net income analysis to portend IR drop at mingled floorplan stages onboth complete and half(prenominal) power nets in the design.To perform power interlock analysis, use the analyze_fp_rail command.To add realistic pads, use the create_fp_virtual_pad command.To trend the hard macro blockages, use the set_fp_power_plan_constraints command. think the psychoanalysis ResultsWhen power and rail analysis are complete, one fecal matter check for the voltage drop and electromigration violations in the design by using the voltage drop map and the electromigration map. champion buttocks save the results of voltage drop and electromigration topical minginess set to the database by thrift the CEL view that has just been analyzed. report places for Power communicate deductive reasoning and Power lucre abbreviation StrategiesTo get a report of the current determine of the strategies utilize by power communicate tax deductionand power network analysis by using the report_fp_rail_strategy command. 165.9 execute simulacrum orbiculate Routing star can perform prototype orbicular routing to get an estimate of the routability and congestion of the design. world(prenominal) routing is through with(p) to mark possible congestion hot spy that might pull through in the floorplan receivable to the placement of the hard macros or shortsighted channel spacing.To perform world-wide routing, use the route_fp_proto command.5.10 do graded clock supplyThis section describes how to reduce timing closure iterations by performing vertical clock planning on a top-level design during the early stages of the virtual flat flow, after plan groups are created and before the hierarchy is committed. ace can perform clock planning on a specify clock net or on all clock nets in the design. Setting clock intend OptionsTo set clock planning options, use the set_fp_clock_plan_options command. playacting quantify formulation operationsTo perform clock planning operations, use the compile_fp_clock_plan command. Generating time manoeuvre ReportsTo sacrifice clock channelize reports, use the report_clock_ corner command. use Multivoltage Designs in time trainingclock planning supports multivoltage designs. Designs in multivoltage domains operate at various voltages. Multivoltage domains are connected through level-shifter cells. A level-shifter cell is a special cell that can carry signals across dissimilar voltage areas. playacting figure Group-Aware clock manoeuver entailment in measure homeworkWith this feature, clock channelize synthesis can generate a clock manoeuver that honors the plan groups sequence inserting buffers in the tree and prevent new clock buffers from world rig id on top of a plan group unless they travail the entire subtree internal that particular plan group. This results in a minimum of clock feedthroughs, which makes the design easier to have sex during dislocation and budgeting. 165.11 execute In-Place optimizationIn-place optimization is an reiterative process that is based on virtual routing. terce types of optimizations are performed timing improvement, area recovery, and stamping ground DRC violations. These optimizations prese